`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/20 09:56:19
// Design Name: 
// Module Name: fifo2axi
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module fifo2axi(
		//! AXI
		// Master Write Address
		output [0:0]  M_AXI_AWID,
		output [31:0] M_AXI_AWADDR,
		output [7:0]  M_AXI_AWLEN,    // Burst Length: 0-255
		output [2:0]  M_AXI_AWSIZE,   // Burst Size: Fixed 2'b011
		output [1:0]  M_AXI_AWBURST,  // Burst Type: Fixed 2'b01(Incremental Burst)
		output        M_AXI_AWLOCK,   // Lock: Fixed 2'b00
		output [3:0]  M_AXI_AWCACHE,  // Cache: Fiex 2'b0011
		output [2:0]  M_AXI_AWPROT,   // Protect: Fixed 2'b000
		output [3:0]  M_AXI_AWQOS,    // QoS: Fixed 2'b0000
		output [0:0]  M_AXI_AWUSER,   // User: Fixed 32'd0
		output        M_AXI_AWVALID,
		input         M_AXI_AWREADY,

		// Master Write Data
		output [63:0] M_AXI_WDATA,
		output [7:0]  M_AXI_WSTRB,
		output        M_AXI_WLAST,
		output [0:0]  M_AXI_WUSER,
		output        M_AXI_WVALID,
		input         M_AXI_WREADY,

		// Master Write Response
		input [0:0]   M_AXI_BID,
		input [1:0]   M_AXI_BRESP,
		input [0:0]   M_AXI_BUSER,
		input         M_AXI_BVALID,
		output        M_AXI_BREADY,

		// Master Read Address
		output [0:0]  M_AXI_ARID,
		output [31:0] M_AXI_ARADDR,
		output [7:0]  M_AXI_ARLEN,
		output [2:0]  M_AXI_ARSIZE,
		output [1:0]  M_AXI_ARBURST,
		output [1:0]  M_AXI_ARLOCK,
		output [3:0]  M_AXI_ARCACHE,
		output [2:0]  M_AXI_ARPROT,
		output [3:0]  M_AXI_ARQOS,
		output [0:0]  M_AXI_ARUSER,
		output        M_AXI_ARVALID,
		input         M_AXI_ARREADY,

		// Master Read Data 
		input [0:0]   M_AXI_RID,
		input [63:0]  M_AXI_RDATA,
		input [1:0]   M_AXI_RRESP,
		input         M_AXI_RLAST,
		input [0:0]   M_AXI_RUSER,
		input         M_AXI_RVALID,
		output        M_AXI_RREADY,

		//! FIFO
		input			wr_clk,
		input			fifo_wr_en,
		input	[63:0]	fifo_din,
		output			fifo_full,
		output			fifo_almost_full,
		output			fifo_wr_rst_busy,

		//! CTRL signal
		input			M_AXI_ACLK,
		input			rst_n,
		output			fifo_empty,

		input [2:0]		intr_state,
		output			axi_busy,
		input			trigger,
		input [31:0]	pl_cnt,
		input [31:0]	pl_adr
	);

//! FIFO
wire		fifo_rd_en;
wire [63:0]	fifo_dout;
wire		fifo_almost_empty;
wire		fifo_rd_rst_busy;
wire [12:0]	fifo_rd_data_count;

//! local bus
wire 		WR_READY;
wire 		WR_DONE;
wire 		WR_START;
wire [31:0]	WR_ADRS;
wire [31:0]	WR_LEN;

//! 例化 FIFO
fifo_generator u_fifo_generator (
  .rst(~rst_n),                      // input wire rst

  //write
  .wr_clk(wr_clk),                // input wire wr_clk
  .din(fifo_din),                      // input wire [63 : 0] din
  .wr_en(fifo_wr_en),                  // input wire wr_en
  .full(fifo_full),                    // output wire full
  .almost_full(fifo_almost_full),      // output wire almost_full
  .wr_rst_busy(fifo_wr_rst_busy),      // output wire wr_rst_busy

  //read
  .rd_clk(M_AXI_ACLK),                // input wire rd_clk
  .dout(fifo_dout),                    // output wire [63 : 0] dout
  .rd_en(fifo_rd_en),                  // input wire rd_en
  .empty(fifo_empty),                  // output wire empty
  .almost_empty(fifo_almost_empty),    // output wire almost_empty
  .rd_data_count(fifo_rd_data_count),  // output wire [12 : 0] rd_data_count
  .rd_rst_busy(fifo_rd_rst_busy)      // output wire rd_rst_busy
);

//! 例化 axi_ctrl
axi_ctrl  u_axi_ctrl (
    .clk                     ( M_AXI_ACLK        	      ),
    .rst_n                   ( rst_n                      ),
    .trigger                 ( trigger                    ),
    .intr_state              ( intr_state          [2:0]  ),
    .pl_cnt                  ( pl_cnt              [31:0] ),
    .pl_adr                  ( pl_adr              [31:0] ),
    .wr_ready                ( WR_READY                   ),
    .wr_done                 ( WR_DONE                    ),
    .fifo_rd_data_count      ( fifo_rd_data_count  [12:0] ),

    .wr_start                ( WR_START                   ),
    .wr_adrs                 ( WR_ADRS             [31:0] ),
    .wr_len                  ( WR_LEN              [31:0] )
);

//! 例化 axi_master
axi_master u_axi_master
(
	.ARESETN(rst_n),
	.ACLK(M_AXI_ACLK),
	
	.M_AXI_AWID(M_AXI_AWID),
	.M_AXI_AWADDR(M_AXI_AWADDR),     
	.M_AXI_AWLEN(M_AXI_AWLEN),
	.M_AXI_AWSIZE(M_AXI_AWSIZE),
	.M_AXI_AWBURST(M_AXI_AWBURST),
	.M_AXI_AWLOCK(M_AXI_AWLOCK),
	.M_AXI_AWCACHE(M_AXI_AWCACHE),
	.M_AXI_AWPROT(M_AXI_AWPROT),
	.M_AXI_AWQOS(M_AXI_AWQOS),
	.M_AXI_AWUSER(M_AXI_AWUSER),
	.M_AXI_AWVALID(M_AXI_AWVALID),
	.M_AXI_AWREADY(M_AXI_AWREADY),
	
	.M_AXI_WDATA(M_AXI_WDATA),
	.M_AXI_WSTRB(M_AXI_WSTRB),
	.M_AXI_WLAST(M_AXI_WLAST),
	.M_AXI_WUSER(M_AXI_WUSER),
	.M_AXI_WVALID(M_AXI_WVALID),
	.M_AXI_WREADY(M_AXI_WREADY),
	
	.M_AXI_BID(M_AXI_BID),
	.M_AXI_BRESP(M_AXI_BRESP),
	.M_AXI_BUSER(M_AXI_BUSER),
	.M_AXI_BVALID(M_AXI_BVALID),
	.M_AXI_BREADY(M_AXI_BREADY),
	
	.M_AXI_ARID(M_AXI_ARID),
	.M_AXI_ARADDR(M_AXI_ARADDR),
	.M_AXI_ARLEN(M_AXI_ARLEN),
	.M_AXI_ARSIZE(M_AXI_ARSIZE),
	.M_AXI_ARBURST(M_AXI_ARBURST),
	.M_AXI_ARLOCK(M_AXI_ARLOCK),
	.M_AXI_ARCACHE(M_AXI_ARCACHE),
	.M_AXI_ARPROT(M_AXI_ARPROT),
	.M_AXI_ARQOS(M_AXI_ARQOS),
	.M_AXI_ARUSER(M_AXI_ARUSER),
	.M_AXI_ARVALID(M_AXI_ARVALID),
	.M_AXI_ARREADY(M_AXI_ARREADY),
	
	.M_AXI_RID(M_AXI_RID),
	.M_AXI_RDATA(M_AXI_RDATA),
	.M_AXI_RRESP(M_AXI_RRESP),
	.M_AXI_RLAST(M_AXI_RLAST),
	.M_AXI_RUSER(M_AXI_RUSER),
	.M_AXI_RVALID(M_AXI_RVALID),
	.M_AXI_RREADY(M_AXI_RREADY),

	
	.MASTER_RST(~rst_n),
	
	.WR_START(WR_START),
	.WR_ADRS(WR_ADRS),
	.WR_LEN(WR_LEN),
	.WR_READY(WR_READY),
	.WR_BUSY(axi_busy),
	.WR_DONE(WR_DONE),

	.WR_FIFO_RE(fifo_rd_en),
	.WR_FIFO_EMPTY(fifo_empty),
	.WR_FIFO_AEMPTY(fifo_almost_empty),
	.WR_FIFO_DATA(fifo_dout),
	.WR_FIFO_RST_BUSY(fifo_rd_rst_busy)
);

endmodule
